BUS DEFINITION Revision B:

1        +5V                                    _____________
2         Data 0                               |                       |
3        Data 1                                |                       |
4        Data 2                                |                       |
5        Data 3                                |Component       |
6        Data 4                                |Side                 |
7        Data 5                                |                       |
8        Data 6                                |1……….....30  |
9        Data 7                                |_____________|
10      Q
11      TPA
12      TPB
13      -MRD
14      -MRW
15      Address 0
16      Address 1
17      Address 2
18      Address 3
19      Address 4
20      Address 5
21      Address 6
22      Address 7
23      -Interrupt
24      N2
25      -EF
26      -VMA
27      -RESET
28      N1
29      N0
30      GND

Most signals are connected directly from the 1802 are unbuffered.

-EF: is connected to one of EF1-4 via a jumper block on the CPU card

-VMA (Valid Memory Address): is used to support directing the CPU to an address other then 0x0000 at reset. -VMA is an active low signal indicating the address on the bus is valid. Immediately after a reset the VMA circuit on the CPU card may, depending on the VMA mode selected by a jumper block, hold VMA high forcing the CPU to read on board memory remapped to 0x0000. Memory selection circuits must combine this signal with any other address information during decoding. Once asserted low VMA may go high at any time indicating the CPU is using on board memory. (See CPU Design for more information on VMA modes)

-RESET: is an active low signal other cards can use as a reset signal

1