CPU Rev. A operational description

Last Updated: October 31, 2005 11:13:27 AM

Bus Buffering: All required CPU signals are passed directly to the bus with no buffering Mode Control: 74LS20 IC3 and IC4 create a 4 input 2 out mode control to drive 1802 -WAIT and -CLEAR lines. Each of  IC3 and IC4 create a SR flip flop, one for -WAIT and one for -CLEAR. The four signals -RUN, -RESET, -LOAD, -PAUSE  are inputs to the SR flip flops, each input line has a 10K pull up. SR Flip flops work by receiving a low input pulse on  either the upper gate (Set) or the lower gate (reset). It is important any lines driving the 4 mode control inputs are open collector, that way multiple circuits such as front panel can also drive these lines.

Mode Control Logic
Mode IC3A












Reset L     L H L
Run L   L   H H
Wait/Pause   L L   L H
Load   L   L L L
L = Low pulse, not held low

Reset: CM1232 U1 provides a power on reset pulse (low) signal when power is first applied. The -RST input of U1 is open collector. This reset signal is also routed to a 74LS123 IC5 one shot pulse generator which generates a low pulse on the -RUN input to mode control at the completion of the reset pulse. The 74LS123 output Pin 13 is connected to the -RUN line via an open collector inverter. CM1232 U1 also supports a push button reset which is connected to both S1 and SV1 to allow connection to the reset switch from the old wire wrap Front Panel card.

Clock generator: The clock generator is made up 3 NAND gates IC7 gates A, B, and C.  74LS74 IC8 gate A divides the clock by 2. LCLK is an inverted version of the CPU clock, this signal is used by the 1861.

Address expansion: 74LS373 IC1 demultiplexes address A0-7 into A8-A15 using TPA.

4K Bank Select: IC9 74LS138 3 to 8 decoder determines which 4K block of memory to map the EPROM to. IC9 takes A12, A13, and A14 on the decoder input as well as A15 connected to -enable (pin 4) or enable (pin 6) depending if the EPROM is to be mapped to the upper or lower 32K address range as set by SV2. SV4 is used to jumper a decoder output to the EPROM enable logic (see jumpers section below).

EPROM: Data D0-7 is connect directly to CPU D0-7, Address A0-A7 is connect to CPU A0-A7, A8-A12 is connected to address expansion IC1. CPU  -OE (output enable) on the EPROM.

VMA and EPROM chip enable: IC8B 74LS74 flip flop is reset when -RESET is active low. First access to memory with A15 high sets the flip flop (stays set until next reset). If VMA is boot only -Q output of flip flop is connected to VMA, before access to A15 -Q is high and therefore EPROM chip enable is low after inverter IC6B 74LS05, after access to A15 -Q goes low and VMA is always valid (low) and therefore EPROM is not enabled. If VMA is boot/remap EPROM select (active low) is combined with flip flop Q output via a nand gate to generate VMA and EPROM chip enable.

EPROM Select from SV4 IC9B 74LS74 Q VMA

Active lo (0 = active)


Active Lo (0 = active)

1 0

Before A15 access

1 0
0 0

Before A15 access

1 0
1 1

After A15 Access


Bus address valid

0 1

After A15 Access

1 0

If VMA is No ROM, then VMA is always valid (low) and EPROM is never enabled.

Jumper Blocks:
JP1: Selects which one of -EF1-4 is routed to the bus
JP2: Selects which one of -EF1-4 is routed to the Front Panel card
JP3: Selects which one of -EF1-4 is routed to the 1861/Keyboard Card for 1861 support
JP4: Selects which one of -EF1-4 is routed to the 1861/Keyboard Card for Keyboard character available flag
SV2: Selects if the EPROM is mapped to upper or lower 32K address bank, this block uses two parallel jumpers,  
connect either the "H" pins to the center pins or the "L" pins to the center pins. Default is "H".
SV4: Selects which 4K bank within the 32 bank, selected by SV5, the EPROM occupies. See silk screen for layout. Bank
7 is 0x7000, bank 0 is 0x0000 (plus the state of SV5 which determines A15). Default is bank 7, therefore the default
EPROM address is 0xF000 - 0xFFFF.
SV5: VMA Mode, selects if the on board EPROM will be enabled:
1) "Boot only" Map on board EPROM to 0x0000 and enable on board EPROM access until the first access to an address
above 0x8000 and then disable on board EPROM.
2) "Boot/REMAP" Map on board EPROM to 0x0000 and enable on board EPROM access until the first access to an
address aboce 0x8000 then remap EPROM to address range set by SV2 and SV4.
3) "No ROM" EPROM is never mapped and first access to 0x0000 is to the bus.

SV1: External reset on pin 1, active low, connected to U1 CM1232 pushbutton input
SV3: 1861/Keyboard Card connector
SV6: Front Panel Card connector

LED1/PWR connects directly card power
LED2/Wait displays CPU -WAIT line status
LED3/CLEAR displays CPU -CLEAR line status
LED4/Q displays CPU Q line status
LED5/VMA displays bus VMA status (On - bus contains valid address)