Memory Rev. A operational description

Last Updated: November 09, 2005 09:48:34 PM

Bus Buffering: 4050 Gates 7A-F and 8A-D buffer the bus address A0-7 and -MRD -MWR lines.

Address expansion: 4042 IC6 and IC9 demultiplex address A0-7 into A8-A15 using TPA. IC9 provide both A15 and -A15 required for 32K chip selection.

Chip Selection: 74LS32 IC14 Gate A generates chip select for the lower 32K (0x0000 - 0x7ffff) address range RAM 1 and EPROM 1. Chip select is generated by combining a low on A15 and active low on bus signal -VMA (see bus defintion for more information on -VMA). Gate B generates chip select for RAM 2 and EPROM 2 using -A15 from IC9 and bus signal -VMA.

4K Bank Select: Each 4K block of the RAM and EPROM chips can be enabled or disabled from the memory map via a 74LS151. Each 8 to 1 74LS151  multiplexer is connect to A12, A13, A14 and a 32K bank select input. Each of the eight multiplexer inputs is connected to either GND or VCC. A12, A13, A14 select the multiplexer input which is connected to the RAM or EPROM chip enable.

EPROM and RAM: Data D0-7 is connect directly to bus D0-7, Address A0-A7 is connect to buffered A0-A7, A8-A14 is connected to address expansion IC6 and IC9.  Buffered -MRD is connected to -RD on the RAM and -OE (output enable) on the EPROM. On the RAM -WR is connect to buffered -MWR.